/**
 * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved.
 */

#ifndef VPC_DRV_VPC_COMM_H
#define VPC_DRV_VPC_COMM_H

#include "dvpp_cmdlist_num_define.h"
#include "dvpp_cmdlist.h"
#include "dvpp_decoder.h"
#include "vpc_pipeline/pipeline_module.h"

#define SET_MULTI_REG_OFFSET 24U

#define VP_WR_CFG 0U
#define VP_WR_AXI_LINE 1U
#define VP_WR_LWG 2U
#define VP_WR_HIGH_ADDR 3U
#define VP_WR_LOW_ADDR 4U
#define VP_RD_CFG 0U
#define VP_RD_LWH 1U
#define VP_RD_FHG 2U
#define VP_RD_AXI_LINE 3U
#define VP_RD_HIGH_ADDR 4U
#define VP_RD_LOW_ADDR 5U

#define SIDE_CHN0 1U
#define SIDE_CHN1 2U

int32_t drv_vpc_struct_assign(dvpp_decoder *decoder, uint32_t node_idx,
    void *dst, const uint16_t struct_len, uint32_t type);
void drv_vpc_config_sqe(struct CmdBuf *cmd_buf, enum dvpp_sqe_ptr_mode mode, uint32_t blkdim, struct dvpp_sqe *sqe);
void drv_vpc_config_sqelist(struct CmdBuf *cmd_buf, uint32_t sqe_idx, uint32_t blkdim);
void drv_vpc_build_cmdnode(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_cmdnode_set_next_node(struct CmdBuf *cmd_buf, struct CmdNode *node);
void drv_vpc_cmdnode_connect_last_node(struct CmdBuf *cmd_buf);

uint8_t drv_vpc_get_yuvscaler_half_line_mode(uint64_t iv, uint32_t hsize);
void drv_vpc_cmdnode_config_interrupt(struct CmdNode *node);
void drv_vpc_cmdnode_clear_interrupt(struct CmdNode *node);
void drv_vpc_cmdnode_config_interrupt(struct CmdNode *node);
void drv_vpc_cmdnode_connect_last_node(struct CmdBuf *cmd_buf);
void drv_vpc_cmdnode_config_writeback_front(struct CmdNode *pos_node, struct CmdNode *pre_node);

void drv_vpc_config_cmdnode_reverse_space(struct CmdNode *node);
void drv_vpc_config_cmdnode_top(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_in_swap(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_out_swap(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx, uint32_t chn);
void drv_vpc_config_cmdnode_uvup(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_csc(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_in0_uvdown(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_out_uvdown(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx, uint32_t chn);
void drv_vpc_config_cmdnode_xflip(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_precrop(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_postcrop(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_resize(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx, uint32_t chn);
void drv_vpc_config_cmdnode_prepadding(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_postpadding(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx, uint32_t chn);
void drv_vpc_config_cmdnode_affine(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_lut(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_blending(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_filter_control(struct CmdNode *node, struct Filter *filter);
void drv_vpc_config_cmdnode_filter(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_frame_start(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_vlc(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_head(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
void drv_vpc_config_cmdnode_histogram(dvpp_decoder *decoder, struct CmdNode *node, uint32_t node_idx);
#endif // #ifndef VPC_DRV_VPC_COMM_H
